1. Field of Invention
This invention relates to a multi-chips stacked package. More particularly, the present invention is related to a multi-chips stacked package having a carrier for carrying the upper chip for preventing the upper chip from being directly disposed on the lower chip.
2. Related Art
Recently, integrated circuit (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Due to the assembly package in miniature and the integrated circuits operation in high frequency, MCM (multi-chips module) packages are commonly used in said assembly packages and electronic devices. Usually, said MCM package mainly comprises at least two chips encapsulated therein, for example a processor unit, a memory unit and related logic units, so as to upgrade the electrical performance of said assembly package. In addition, the electrical paths between the chips in said MCM package are short so as to reduce the signal delay and save the reading and writing time.
Generally speaking, conventional MCM packages shall be a multi-chips side-by-side package or a multi-chips stacked package. As shown in FIG. 1, it illustrates a multi-chips stacked package and said stacked package is formed by disposing upper chips 12 and 13 on a lower chip 14 by wire-bonding and chip-stacking technology, electrically connecting the upper chips 12 and 13 to a substrate 16 respectively and electrically connecting the upper chips 12 and 13 with each other via the electrically conductive wires 18. However, the upper chip 12 is partially disposed on the lower chip 14 and overhangs over the lower chip 14. Similarly, the upper chip 13 is also partially disposed on the lower chip 14 and overhangs over the lower chip 14. Thus, the upper chips 12 and 13 will be damaged and cracked more easily in the operation of the wire-bonging process. Referring to FIG. 2, lower chips 22 and 23 are disposed on the substrate 26, and the upper chip 24 is mounted on the lower chips 22 and 23 simultaneously so that the upper chip 24 can be supported firmly by the lower chips 22 and 23 and the substrate 26, and prevented from being damaged and cracked.
As mentioned above, however, there are several disadvantages as following shown. When the lower chips 22 and 23 are adjacent to each other and connect with each other, the lower chip 22 will be pressed against the lower chip 23 due to thermal expansion. Thus, in order to prevent the above-mentioned problem, the lower chips 22 and 23 shall be apart from each other in a distance. However, when the distance between the lower chips 22 and 23 is larger than 50 μm, the portion 242 of the lower surface of the upper chip 24 not supported by the lower chips 22 and 23 will be damaged easily in the performance of the wire-bonding process.
Therefore, providing another assembly package to solve the mentioned-above disadvantages is the most important task in this invention.